In the design of a system-on-chip, there are several design methodologies such as design for test (DFT), design for manufacturing (DFM), and design for debug (DFD), collectively known as DFX, for example, that can be used to increase the testability, fault coverage and manufacturing yield of the system-on-chip. Scan insertion, or the conversion of flip-flops into scan flip-flops to form scan chains, is a common technique used in digital integrated circuit design to allow production testers to check for any manufacturing faults of the integrated circuit using the aid of the scan chains.
FIG. 1 illustrates a block diagram 100 of a prior art system-on-chip 105. The prior art system-on-chip 105 has a processor 110 with a clock (CLK) unit 112 that provides a CLK 114 to the logic block 1 120 and the logic block 2 130. The prior art system-on-chip 105 also has a CLK unit 160 that provides a CLK 162 to the logic block 3 140. The input/output (I/O) block 150 controls the external access(es) to the prior art system-on-chip 105.
However, for the design of the prior art system-on-chip 105, scan insertion poses a potential problem as the current scan insertion techniques are not scalable and any addition of extra scan blocks or chains during the end stages of the design requires extensive and time-consuming changes. The current scan testing technique often bypasses a memory array(s) in the logic blocks using the scan flip-flops. The scan flip-flops inserted to bypass the memory arrays not only require additional chip area, they also do not allow scan testing to be performed through the memory arrays.